// ----------------------------------------------------------------------
// Include files
// ----------------------------------------------------------------------
#include	<string.h>
#include	"video.h"

#if	defined(__USE_CMOS_MN34420__)
// ----------------------------------------------------------------------
// Struct/Union Types and define
// ----------------------------------------------------------------------

// ----------------------------------------------------------------------
// Static Global Data section variables
// ----------------------------------------------------------------------

//#define LAMP_PATTERN
// ----------------------------------------------------------------------
// External Variable 
// ----------------------------------------------------------------------

// ----------------------------------------------------------------------
// Static Prototype Functions
// ----------------------------------------------------------------------
static void INIT_Normal_4CH_MODE(void);

// ----------------------------------------------------------------------
// Static functions
// ----------------------------------------------------------------------

// ----------------------------------------------------------------------
// Exported functions
// ----------------------------------------------------------------------

//--------------------------------------------------------------------------------------------------------------------------
void MN34420_Initialize(void)
{
	INIT_Normal_4CH_MODE();
#if defined(__USE_CMOS_MN34422__)		
	UARTprintf("MN34422_Initialize\n\r");
#else
	UARTprintf("MN34420_Initialize\n\r");
#endif
}

//--------------------------------------------------------------------------------------------------------------------------
static void INIT_Normal_4CH_MODE(void)
{

#if defined(__USE_MN34420_SLAVE_MODE__)
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x300C, 0x08A0);		//slave mode
#else
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x300C, 0x0820);		//Master mode
#endif

	CMOS_WordWrite(SPI_MN34420_ADDR, 0x300E, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3002, 0x1084);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3004, 0x1042);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3006, 0x0200);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3008, 0x1580);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x300A, 0xEF30);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3000, 0x0103);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3000, 0x0153);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x300E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3200, 0x3F06);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3202, 0x0B0B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3204, 0x1400);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3206, 0xA778);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3208, 0x4900);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x320A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3010, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3012, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3014, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3016, 0x00F0);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3018, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x301A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x301C, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x301E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3020, 0x001A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3022, 0x3800);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3024, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3026, 0x2000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3028, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x302A, 0xFF9F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x302C, 0x0804);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x302E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3030, 0x5E05);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3032, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3034, 0x0060);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3036, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3038, 0x0060);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x303A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x303C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3040, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3042, 0x4210);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3044, 0x0300);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3046, 0x4900);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3048, 0x0030);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x304A, 0xE201);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x304C, 0x3133);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x304E, 0x2233);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3050, 0x0050);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3052, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3054, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3056, 0x0400);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3058, 0x7F7F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x305A, 0x7F03);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3060, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3062, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3100, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3102, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3104, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3106, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3108, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x310A, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x310C, 0x0016);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3110, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3112, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3114, 0x0016);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3116, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3118, 0x0120);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x311A, 0x0016);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x311C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3120, 0x003C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3122, 0x047F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3124, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3126, 0x0454);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3130, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3140, 0x00E0);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3142, 0x00C7);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3150, 0x0040);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3152, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3154, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3156, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3158, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3160, 0x0040);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3162, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3164, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3166, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3168, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3170, 0x0800);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3172, 0x0800);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4000, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4002, 0x0107);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4004, 0x0013);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4006, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4008, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x400A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x400C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x400E, 0x0800);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4010, 0x0400);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4012, 0x0025);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4014, 0x1710);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4016, 0x40FF);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4018, 0xC000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x401A, 0x0029);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x401C, 0x0029);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x401E, 0x002B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4020, 0x002A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4022, 0x002A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4024, 0x002E);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4026, 0x002D);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4028, 0x002C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x402A, 0x0024);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x402C, 0x0027);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x402E, 0x0026);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4030, 0x0023);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4032, 0x0024);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4034, 0x0025);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4036, 0x0022);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4038, 0x0023);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x403A, 0x0066);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x403C, 0x0062);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x403E, 0x0063);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4040, 0x0066);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4042, 0x0066);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4044, 0x0066);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4046, 0x006C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4048, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x404A, 0x1F1F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x404C, 0x1F06);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x404E, 0x0812);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4050, 0x0F0C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4052, 0x0B0A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4054, 0x0807);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4056, 0x0604);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4058, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x405A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x405C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x405E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4060, 0xFF07);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4062, 0x7700);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4064, 0x4400);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4066, 0x0C0C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4068, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x406A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x406C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x406E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4070, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4072, 0x0000);
#if defined(__USE_CMOS_MN34442__)							//version 1.30(17/11/16)
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4100, 0x102A);		
#else
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4100, 0x1032);		
#endif
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4102, 0x5476);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4104, 0x8B09);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4106, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4108, 0x0A88);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x410A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x410C, 0x0082);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x410E, 0x2200);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4110, 0x0022);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4112, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4114, 0x3F33);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4116, 0xF63F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4118, 0x1C15);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x411A, 0x2600);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x411C, 0xBA00);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x411E, 0x0022);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4120, 0x0200);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4122, 0x4000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4124, 0x6088);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4126, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4128, 0x9099);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x412A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x412C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x412E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4130, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4132, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4134, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4136, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4138, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x413A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x413C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x413E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4140, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4142, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4144, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4146, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4148, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x414A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x414C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x414E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4150, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4152, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4154, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4156, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4158, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x415A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x415C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x415E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4200, 0x2143);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4202, 0x6598);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4204, 0x0A00);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4206, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4208, 0x08AA);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x420A, 0x880A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x420C, 0xA000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x420E, 0x22A8);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4210, 0x0200);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4212, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4214, 0xF007);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4216, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4218, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x421A, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x421C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x421E, 0x0200);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4220, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4222, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4224, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4226, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4228, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x422A, 0x21AA);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x422C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x422E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4230, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4232, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4234, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4236, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4238, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x423A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x423C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x423E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4240, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4242, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4244, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4246, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4248, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x424A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x424C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x424E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4250, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4252, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4254, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4256, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4258, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x425A, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x425C, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x425E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4260, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4262, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4264, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4266, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4268, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4300, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4302, 0x0464);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4304, 0x0671);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4306, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4308, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x430A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x430C, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x430E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4310, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4312, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4314, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4316, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4318, 0x2307);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x431A, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x431C, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x431E, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4320, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4322, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4324, 0x0461);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4326, 0x042D);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4328, 0x0460);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x432A, 0x0456);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x432C, 0x0457);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x432E, 0x045F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4330, 0x0460);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4332, 0x0461);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4334, 0x0461);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4336, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4338, 0x1000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x433A, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x433C, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x433E, 0x5353);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4340, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4342, 0x003C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4344, 0x0006);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4346, 0x0200);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4348, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x434A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x434C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x434E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4350, 0x000F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4352, 0x005A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4354, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4356, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4358, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4360, 0x0039);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4400, 0xBE67);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4402, 0x0052);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4404, 0x000F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4406, 0x0183);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4408, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x440A, 0x181B);
#if defined(__USE_CMOS_MN34422__)							//version 1.20(17/8/31)
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x440C, 0x0042);
//	CMOS_WordWrite(SPI_MN34420_ADDR, 0x440C, 0x00C0);		//when wdr mode : 0xC0
#else
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x440C, 0x0000);
#endif
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x440E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4410, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4412, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4414, 0x0006);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4416, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4418, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x441A, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x441C, 0x001B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x441E, 0x000B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4420, 0x0183);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4422, 0x000B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4424, 0x0183);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4426, 0x000B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4428, 0x0183);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x442A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x442C, 0x0107);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x442E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4430, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4432, 0x0108);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4434, 0x0107);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4436, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4438, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x443A, 0x0008);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x443C, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x443E, 0x0008);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4440, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4442, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4444, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4446, 0x0209);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4448, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x444A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x444C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x444E, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4450, 0x0183);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4452, 0x0300);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4454, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4456, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4458, 0x0018);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x445A, 0x1818);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x445C, 0x0000);
#if defined(__USE_CMOS_MN34422__)							//version 1.20(17/8/31)
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x445E, 0x0042);
//	CMOS_WordWrite(SPI_MN34420_ADDR, 0x445E, 0x00C0);		//when wdr mode : 0xC0
#else
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x445E, 0x0000);
#endif
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4460, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4462, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4464, 0x0300);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4466, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4468, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x446A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x446C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x446E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4470, 0x0A00);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4472, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4474, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4476, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4478, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x447A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x447C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x447E, 0x0101);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4480, 0x001B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4482, 0x0019);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4484, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4486, 0x0107);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4488, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x448A, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x448C, 0x0008);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x448E, 0x0107);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4490, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4492, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4494, 0x0108);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4496, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4498, 0x0008);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x449A, 0x000B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x449C, 0x0183);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x449E, 0x000B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44A0, 0x0183);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44A2, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44A4, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44A6, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44A8, 0x1818);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44AA, 0x001B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44AC, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x44AE, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4500, 0x0019);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4502, 0x810B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4504, 0x0073);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4506, 0x0318);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4508, 0x0005);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x450A, 0x008B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x450C, 0xD800);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x450E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4510, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4512, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4514, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4516, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4518, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x451A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x451C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x451E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4520, 0x0F00);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4522, 0x0716);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4524, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4526, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4528, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x452A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x452C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x452E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4530, 0x0C3E);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4532, 0x0D02);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4534, 0x0D04);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4536, 0x000D);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4538, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x453A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x453C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x453E, 0x000D);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4540, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4542, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4544, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4546, 0x000D);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4548, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x454A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x454C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x454E, 0x0B0F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4550, 0x0E0A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4552, 0x0005);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4554, 0x0032);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4556, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4558, 0x0032);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x455A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x455C, 0x020F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x455E, 0x050B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4560, 0x0309);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4562, 0x0718);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4564, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4566, 0x0006);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4568, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x456A, 0x020A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x456C, 0x0006);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x456E, 0x0006);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4570, 0x0508);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4572, 0x0C08);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4574, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4576, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4578, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x457A, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x457C, 0x040D);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x457E, 0x0918);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4580, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4582, 0x0118);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4584, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4586, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4588, 0x0008);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x458A, 0x0D02);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x458C, 0x0D0F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x458E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4590, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4600, 0x0860);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4602, 0x0021);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4604, 0x000F);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4606, 0x00A3);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4608, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x460A, 0x181B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x460C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x460E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4610, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4700, 0x0019);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4702, 0x2E0B);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4704, 0x0024);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4706, 0x0318);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4708, 0x0017);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x470A, 0x00D1);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x470C, 0x1800);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x470E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5000, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5002, 0x07C0);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5004, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5006, 0x000C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5008, 0x0024);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x500A, 0x103C);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x500C, 0x000D);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x500E, 0x1000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5010, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5012, 0x07FF);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5014, 0x0111);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5016, 0x10E4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5018, 0x10E4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x501A, 0x10E4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x501C, 0x11C8);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x501E, 0x1390);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5020, 0x1720);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5022, 0x1868);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5024, 0x10E4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5026, 0x10E4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5028, 0x10E4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x502A, 0x11C8);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x502C, 0x1390);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x502E, 0x1720);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5030, 0x1868);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5032, 0x07FF);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5034, 0x07FF);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5036, 0x2200);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5038, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x503A, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x503C, 0x000A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x503E, 0x01D4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5040, 0x0A0A);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5042, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5044, 0x0130);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5046, 0xC100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5048, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5052, 0x0011);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5054, 0x01A2);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5056, 0x01FF);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x505C, 0x7800);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x505E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5060, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5062, 0x0FFE);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5064, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5066, 0x0100);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5068, 0x0006);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x506A, 0x008E);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x506C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x506E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5070, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5072, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5074, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5076, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5078, 0x0040);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5090, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5096, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5098, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x509A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x509C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x509E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50A0, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50A2, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50A4, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50A6, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50A8, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50D0, 0x5500);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50D2, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50F0, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50F2, 0x4071);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50F4, 0x1171);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50F6, 0x03D0);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50F8, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50FA, 0x0A00);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x50FC, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5100, 0x0005);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5102, 0x0201);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5104, 0x0403);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5108, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x510A, 0x0203);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x510C, 0x0405);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5110, 0x0043);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5112, 0x0300);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5114, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5116, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5118, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x511A, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5120, 0x2C13);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5122, 0x1210);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5124, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5126, 0x0500);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5128, 0x0050);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5130, 0x0314);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5132, 0x0401);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5134, 0x0B08);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5136, 0x0404);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5138, 0x0905);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x513A, 0x0009);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x513C, 0x00E4);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x513E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5140, 0x0454);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5142, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5144, 0x0453);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5146, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5148, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x514A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x514C, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x514E, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5150, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5152, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5154, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5156, 0x0002);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5158, 0x0003);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x515A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x515C, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5160, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5162, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5164, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5166, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5168, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x516A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x516C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x516E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5170, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5172, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5174, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5176, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5178, 0xE400);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x517A, 0x0450);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x517C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x517E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5180, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5182, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5184, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5186, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5188, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x518A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x518C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x518E, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5190, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5192, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5194, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5196, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x5198, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x519A, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x519E, 0xFFFE);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x51A0, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x51A2, 0x0300);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x603C, 0x0000);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x603C, 0x0001);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x6000, 0x04F8);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x6026, 0x04F7);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3000, 0x01D3);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3000, 0x21D3);
}

//--------------------------------------------------------------------------------------------------------------------------
static void stMN34420_SetRate(MN34420_Mode_t mode) {
	// clock divider (300Ah)
	if( (mode==MN34420_NORMAL)&&
		((GetSS_SensorVoutFps()==25)||(GetSS_SensorVoutFps()==30)) )
		CMOS_WordWrite(SPI_MN34420_ADDR, 0x300A, 0xEF30);  // 1080p30
	else
		CMOS_WordWrite(SPI_MN34420_ADDR, 0x300A, 0xCF30);

	// set vcycle (4302h), hcycle (4304h)
	WORD vcycle=(mode==MN34420_DOL2)?1250:1125;
	WORD hcycle;
	switch(mode) {
		case MN34420_DOL2:  hcycle=1440;  break;
		case MN34420_DOL3:  hcycle=1600;  break;
		default: hcycle=((GetSS_SensorVoutFps()==25)||(GetSS_SensorVoutFps()==30))?1650:825;  break;
	}
#if defined(__VTOTAL_CTRL_PAL__)
	if(GetSS_SensorVoutPAL())  vcycle*=1.2f;
#else
	if(GetSS_SensorVoutPAL())  hcycle*=1.2f;
#endif
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4302, vcycle-1);
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x4304, hcycle-1);
}

//--------------------------------------------------------------------------------------------------------------------------
static void stMN34420_SetMode(MN34420_Mode_t mode) {

	// registers about mode change
	static ROMDATA WORD mode_reg_set[][5]={
		// addr,  fhd30,  fhd60,   wdr2,   wdr3
		{0x3002, 0x1084, 0x1084, 0x10B0, 0x10B0},
		{0x3004, 0x1042, 0x1042, 0x1058, 0x1058},
		{0x3008, 0x1580, 0x1580, 0x3580, 0x3580},
//		{0x300A, 0xEF30, 0xCF30, 0xCF30, 0xCF30},  //set by stMN34420_SetRate()
		{0x301C, 0x0100, 0x0100, 0x0000, 0x0000},
		{0x302A, 0xFF9F, 0xFF9F, 0xFF1F, 0xFF1F},
		{0x3030, 0x5E05, 0x5E05, 0x5E05, 0x9E05},
		{0x3042, 0x4210, 0x4210, 0x4210, 0x4200},
		{0x3044, 0x0300, 0x0300, 0x3200, 0x3200},
		{0x3104, 0x0002, 0x0002, 0x0271, 0x0233},
		{0x310C, 0x0016, 0x0016, 0x0001, 0x0119},
		{0x3114, 0x0016, 0x0016, 0x0016, 0x0001},
		{0x400A, 0x0000, 0x0000, 0x0100, 0x0100},
		{0x401A, 0x0029, 0x0029, 0x0038, 0x0038},
		{0x401C, 0x0029, 0x0029, 0x0038, 0x0038},
		{0x401E, 0x002B, 0x002B, 0x0028, 0x0028},
		{0x4020, 0x002A, 0x002A, 0x0038, 0x0038},
		{0x4022, 0x002A, 0x002A, 0x0028, 0x0028},
		{0x4024, 0x002E, 0x002E, 0x0029, 0x0029},
		{0x4026, 0x002D, 0x002D, 0x0029, 0x0029},
		{0x4028, 0x002C, 0x002C, 0x0029, 0x0029},
		{0x402A, 0x0024, 0x0024, 0x0029, 0x0029},
		{0x402C, 0x0027, 0x0027, 0x002B, 0x002B},
		{0x402E, 0x0026, 0x0026, 0x002B, 0x002B},
		{0x4030, 0x0023, 0x0023, 0x002A, 0x002A},
		{0x4032, 0x0024, 0x0024, 0x002E, 0x002E},
		{0x4034, 0x0025, 0x0025, 0x002F, 0x002F},
		{0x4036, 0x0022, 0x0022, 0x002D, 0x002D},
		{0x4038, 0x0023, 0x0023, 0x002D, 0x002D},
		{0x403A, 0x0066, 0x0066, 0x002F, 0x002F},
		{0x403C, 0x0062, 0x0062, 0x002F, 0x002F},
		{0x403E, 0x0063, 0x0063, 0x002E, 0x002E},
		{0x4040, 0x0066, 0x0066, 0x002D, 0x002D},
		{0x4042, 0x0066, 0x0066, 0x0025, 0x0025},
		{0x4044, 0x0066, 0x0066, 0x0027, 0x0027},
		{0x4046, 0x006C, 0x006C, 0x0027, 0x0027},
		{0x420A, 0x880A, 0x880A, 0x880A, 0x800A},
		{0x4300, 0x0000, 0x0000, 0x0010, 0x0020},
//		{0x4302, 0x0464, 0x0464, 0x04E1, 0x0464},  //set by stMN34420_SetRate()
//		{0x4304, 0x0671, 0x0338, 0x059F, 0x063F},  //set by stMN34420_SetRate()
		{0x4308, 0x0000, 0x0000, 0x02CD, 0x0212},
		{0x4326, 0x042D, 0x042D, 0x04AA, 0x042D},
		{0x4332, 0x0461, 0x0461, 0x0000, 0x0000},
		{0x4334, 0x0461, 0x0461, 0x0000, 0x0000},
		{0x4342, 0x003C, 0x003C, 0x003C, 0x0020},
		{0x4400, 0xBE67, 0xBE67, 0xBE67, 0x0667},
		{0x4402, 0x0052, 0x0052, 0x006E, 0x006E},
		{0x4406, 0x0183, 0x0183, 0x00A1, 0x00A1},
		{0x441E, 0x000B, 0x000B, 0x000B, 0x001C},
		{0x4420, 0x0183, 0x0183, 0x00A1, 0x00A1},
		{0x4422, 0x000B, 0x000B, 0x000B, 0x001C},
		{0x4424, 0x0183, 0x0183, 0x00A1, 0x00A1},
		{0x4426, 0x000B, 0x000B, 0x000B, 0x001C},
		{0x4428, 0x0183, 0x0183, 0x00A1, 0x00A1},
		{0x4430, 0x0100, 0x0100, 0x0101, 0x0101},
		{0x4432, 0x0108, 0x0108, 0x0008, 0x0008},
		{0x4450, 0x0183, 0x0183, 0x00A1, 0x00A1},
		{0x4452, 0x0300, 0x0300, 0x0300, 0x0100},
		{0x4464, 0x0300, 0x0300, 0x0300, 0x0000},
		{0x4470, 0x0A00, 0x0A00, 0x0A00, 0x1D00},
		{0x447E, 0x0101, 0x0101, 0x0000, 0x0000},
		{0x4492, 0x0100, 0x0100, 0x0101, 0x0101},
		{0x4494, 0x0108, 0x0108, 0x0008, 0x0008},
		{0x449A, 0x000B, 0x000B, 0x000B, 0x001C},
		{0x449C, 0x0183, 0x0183, 0x00A1, 0x00A1},
		{0x449E, 0x000B, 0x000B, 0x000B, 0x001C},
		{0x44A0, 0x0183, 0x0183, 0x00A1, 0x00A1},
		{0x4502, 0x810B, 0x810B, 0x810B, 0x390B},
		{0x4504, 0x0073, 0x0073, 0x0067, 0x0067},
		{0x450A, 0x008B, 0x008B, 0x00E9, 0x00E9},
		{0x450C, 0xD800, 0xD800, 0x9D00, 0x1800},
		{0x4522, 0x0716, 0x0716, 0x0716, 0x073B},
		{0x4530, 0x0C3E, 0x0C3E, 0x0C3E, 0x0C39},
		{0x50F2, 0x4071, 0x4071, 0x4071, 0x0071},
		{0x50F4, 0x1171, 0x1171, 0x1171, 0x0171},
	};

	int sel=0;
	switch(mode) {
		case MN34420_NORMAL:
			sel=((GetSS_SensorVoutFps()==25)||(GetSS_SensorVoutFps()==30))?1:2;
			break;
		case MN34420_DOL2: sel=3;  break;
		case MN34420_DOL3: sel=4;  break;
	}

	int i;
	for(i=0; i<sizeof(mode_reg_set)/sizeof(mode_reg_set[0]); i++) {
		CMOS_WordWrite(SPI_MN34420_ADDR, mode_reg_set[i][0], mode_reg_set[i][sel]);
	}
}

//--------------------------------------------------------------------------------------------------------------------------
void MN34420_ChangeFps_Normal(void) {
    stMN34420_SetRate(MN34420_NORMAL);
}

//--------------------------------------------------------------------------------------------------------------------------
void MN34420_WDR_Mode(MN34420_Mode_t mode) {
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3000, 0x2153);  //TG reset (H->L) bit.7
	stMN34420_SetRate(mode);  //set Rate(fps)
	stMN34420_SetMode(mode);  //set Mode
	CMOS_WordWrite(SPI_MN34420_ADDR, 0x3000, 0x21D3);  //TG reset (L->H) bit.7
}

//--------------------------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------------------------

#endif	/* __USE_CMOS_MN34420__ */

/*  FILE_END_HERE */
